(1) Field of the Invention
The present invention relates to a Viterbi decoder with a pipeline processing function which performs maximum likelihood decoding of convolutional codes with an improved throughput.
(2) Description of the Related Art
A Viterbi algorithm is well known as a powerful, reliable technique for decoding convolutional codes and is widely used in, for example, satellite communications.
The principles of Verterbi decoding are described in, for example, IEEE TRANSACTIONS ON COMMUNICATIONS TECHNOLOGY, Vol. COM-19, No. 5, OCTOBER 1971 "Convolutional Codes and Their Performance in Communication Systems" A. J. VITERBI. A Viterbi decoder is disclosed in Japanese Unexamined Patent Publication (Kokai) No. 59-19455, published on Jan. 31, 1984.
As is well known and as will be described in detail later, a conventional Viterbi decoder has calculating circuits each having adders for adding "path metrics" and "branch metrics" to obtain new path metrics (path metrics and branch metrics are defined later); a comparator for comparing the new path metrics, and a selector for selecting one of the new path metrics to be output in response to the output of the comparator.
Adding operations to obtain the new path metrics and the comparing operation of the new path metrics are conventionally carried out within one clock cycle period. The clock cycle period is therefore substantially determined by the operating speeds of the adders and the comparator. In other words, the clock cycle period should be more than the adding time plus the comparing time. This results in low throughput of the Viterbi decoder.
Also, the clock signal is commonly used both for the Viterbi decoder and for its peripheral circuits. The clock cycle period determined by the Viterbi decoder is longer than the clock cycle period for the peripheral circuits when they operate independently. This results in lower speeds for the overall circuit.
To overcome this problem, if the peripheral circuits are formed by, for example, transistor-transistor logic circuits (TTL circuits), then the Viterbi decoder should be formed by emitter-coupled logic (ECL) circuits, which have a higher operating speed than the TTL circuits. If the peripheral circuits are formed by, for example, complementary metal-oxide semiconductor (CMOS) elements, then the Viterbi decoder should be formed by TTL circuits, which have a higher operating speed than the CMOS elements. Fabrication of different types of circuits, such as TTL circuits and ECL circuits or CMOS circuits and TTL circuits, on the same semiconductor substrate, however, overly complicates the manufacturing process.
Further, a Viterbi decoder formed by TTL circuits consumes more power per unit TTL element than the peripheral circuits per unit CMOS element. Also, a Viterbi decoder formed by ECL circuits consumes more power per unit ECL element than the peripheral circuits per unit TTL element.